The present invention relates to an improved electrostatic discharge input protection circuit for integrated circuits.
Protection from electrostatic discharge (ESD) is a very important feature on most integrated circuits incorporating insulated gate field effect transistors (IGFET). ESD transient voltages of several thousand volts are easily applied to such integrated circuits during normal handling procedures. Without adequate input protection, these voltages are sufficient to break down the thin gate oxides used on the input IGFETs.
Standard ESD input protection circuits often provide a mechanism whereby one or more transistors break down at voltages higher than the normal operating voltages but lower than the break down voltage of the input gate, and shunt the ESD current safely to ground. An example of such a circuit is shown in FIG. 1, where transistors Q1 and Q2 turn on when a high voltage is applied, protecting any devices attached to terminal 14. The arrangement of FIG. 1 can provide ESD protection of up to several thousand volts.
Such a standard input circuit has a serious limitation when used with certain classes of circuits. After an ESD voltage has been drained off, a small leakage current will flow through transistors Q1 and Q2 during normal operation. Such leakage current is usually small, generally being on the order of tens of nanoamps. However, certain classes of integrated circuits, such as CMOS operational amplifiers, are often specified to draw input current of no more than tens of picoamps. The use of a standard input protection circuits on such linear CMOS parts will protect the parts themselves from damage, but the parts will no longer meet rated specifications after an ESD voltage has been shunted to ground. Therefore, such parts are no longer useful as meeting the specifications used by circuit designers.
It is therefore an object of the present invention to provide an improved ESD input protection circuit which can protect the integrated circuit from high ESD voltages, while reducing or eliminating leakage current which may be drawn by the ESD protection circuit through the input pin.
Therefore, according to the present invention, a unidirectional current device is coupled between the input pin and the ESD protection clamp circuit so that current flows only from the input pin to the clamp circuit. At the junction between the unidirectional device and the clamp circuit, a voltage supply, normally connected to the most positive voltage supplied to the integrated circuit chip, is attached. Thus, as long as the voltage on the input pin is lower than the positive voltage supply, all leakage current drawn by the ESD protection circuit will be taken directly from the supply and not from the input pin. Thus, although leakage current is still drawn, no excess current is drawn through the input pin, and the integrated circuit as a whole will continue to meet design specifications for maximum input current.
The novel features which characterize the present invention are defined by the appended claims. The foregoing and other objects and advantages of the present invention will hereafter appear, and for purposes of illustration, but not of limitation, two preferred embodiments are shown in the accompanying drawings.